The present invention relates to a receiver of a direct sequence spread spectrum system, and more particularly to a timing recovery circuit in a receiver of a direct sequence spread spectrum system.
In realizing a direct sequence spread spectrum (hereinafter referred to as DS/SS) system, initial synchronization and synchronization tracing are required for corresponding pseudo-noise (PN) codes of transmitting and receiving stages. The DS/SS system utilizing a digital matched filter can easily perform initial synchronization and synchronization tracing, but still has problems with clock differences between the transmitting and receiving stages, the influence of fading, etc., which should be compensated for.
FIG. 1 is a block diagram showing a DS/SS system of a prior art.
In FIG. 1, a signal received via an antenna 201 is mixed with the output of a carrier wave generator 203 in a mixer 202, and then is output as an intermediate frequency (IF) signal via a bandpass filter 204. The IF signal is first multiplied by the output of an IF generator 206 in multipliers 205 and 208 for initial synchronization, wherein the in-phase I of the output from IF generator 206 is multiplied in the I-loop and the quadrature-phase Q of the output is multiplied in the Q-loop, thereby obtaining pseudo-noise (PN) signals without IF components. The PN signals of the I-loop and Q-loop are each converted in analog-to-digital converters 211 and 213 via low-pass filters 209 and 210, and then input to matched filters 214 and 215, respectively. Correlation between the output from a reference PN code generator 212 and the received PN signals are obtained via matched filters 214 and 215, and the obtained correlations are squared in squaring units 216 and 217, respectively. Then, the results are summed in an adder 218. By observing the output of adder 218, a peak detector 219 detects a peak in one period of a PN code and a peak position detector 220 outputs the position of the peak. Once the position of the peak value in one period of the PN code is determined, and then one period of the PN code is terminated, the difference between the peak position in the current period (output of peak detector 220) and the peak position in the previous period (output of delay circuit 221) is obtained via a subtractor 222.
At this time, the difference between the peak positions of the current and the previous periods can be considered as the clock differential between the transmitting and receiving stages. Accordingly, by varying the clock of the receiving stage corresponding to the difference, the clocks of the transmitting and receiving stages can be synchronized. In other words, the difference of the peak positions is converted into an analog signal in a digital-to-analog converter 223 and then is input to a voltage controlled oscillator 225 via a loop filter 224. Thus, the system clock which is utilized throughout the receiving stage can be synchronized with the clock of the transmitting stage. Meanwhile, an average value of previous peak position values with respect to several periods from a delay circuit 221 may be employed, in order to obtain more accurate information.
Data is demodulated in a demodulator 227, using the output of matched filter 214 when the peak value of one period is detected in peak detector 219.
Therefore, the conventional receiver adopts an analog circuit for recovering timing, which impedes miniaturization and degrades the reliability of the system.